1 caution: these devices are sensitive to electrostatic discharge; follow proper esd handling procedures. pspice?is a registered trademark of microsim corporation. http://www.intersil.com or 407-727-9207 | copyright intersil corporation 1999 rfp23n06le, RF1S23N06LESM 23a, 60v, 0.065 ohm, logic level, n-channel power mosfets these n-channel power mosfets are manufactured using a modern process. this process, which uses feature sizes approaching those of lsi circuits, gives optimum utilization of silicon, resulting in outstanding performance. they were designed for use in applications such as switching regulators, switching converters, motor drivers, and relay drivers. these transistors can be operated directly from integrated circuits. formerly developmental type ta49165. features 23a, 60v ? ds(on) = 0.065 ? temperature compensating pspice model peak current vs pulse width curve uis rating curve 175 o c operating temperature related literature - tb334 ?uidelines for soldering surface mount components to pc boards symbol packaging ordering information part number package brand rfp23n06le to-220ab fp23n06l RF1S23N06LESM to-263ab f23n06le note: when ordering, use the entire part number. add the suffix 9a to obtain the to-263ab variant in tape and reel, i.e. RF1S23N06LESM9a. d g s jedec to-220ab jedec to-263ab gate drain (flange) source drain drain (flange) gate source data sheet october 1999 file number 4077.4 no t recommended for new designs recommended p ossib le replacements: rfp23n06le: see huf76419p3 RF1S23N06LESM: see huf76419s3s
2 absolute maximum ratings t c = 25 o c, unless otherwise specified rfp23n06le, RF1S23N06LESM units drain to source voltage (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v dss 60 v drain to gate voltage (r gs = 20k ?) (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v dgr 60 v gate to source voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v gs 10 v continuous drain current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i d pulsed drain current (note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i dm 23 refer to peak current curve a pulsed avalanche rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .e as refer to uis curve power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .p d derate above 25 o c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 0.5 w w/ o c operating and storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .t j , t stg -55 to 175 o c maximum temperature for soldering leads at 0.063in (1.6mm) from case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t l package body for 10s, see techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t pkg 300 260 o c o c caution: stresses above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio n of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not implied. note: 1. t j = 25 o c to 150 o c. electrical speci?ations t c = 25 o c, unless otherwise speci?d parameter symbol test conditions min typ max units drain to source breakdown voltage bv dss i d = 250 a, v gs = 0v 60 - - v gate to threshold voltage v gs(th) v gs = v ds , i d = 250 a1--v zero gate voltage drain current i dss v ds = 55v, v gs = 0v - - 1 a v ds = 50v, v gs = 0v, t c = 150 o c - - 250 a gate to source leakage current i gss v gs = 10v - - 10 a drain to source on resistance (note 2) r ds(on) i d = 23a, v gs = 5v (figure 11) - - 0.065 ? turn-on time t on v dd = 30v, i d = 23a, r l = 1.30 ?, v gs = 5v, r gs = 2.5 ? (figures 15, 18, 19) - - 160 ns turn-on delay time t d(on) -12 - ns rise time t r -93 - ns turn-off delay time t d(off) -28 - ns fall time t f -38 - ns turn-off time t off - - 100 ns total gate charge q g(tot) v gs = 0v to 10v v dd = 48v, i d = 23a, r l = 2.09 ?, i g(ref) = 0.45ma (figures 15, 20, 21) -3848nc gate charge at 5v q g(5) v gs = 0v to 5v - 20 25 nc threshold gate charge q g(th) v gs = 0v to 1v - 0.90 1.2 nc input capacitance c iss v ds = 25v, v gs = 0v, f = 1mhz - 850 - pf output capacitance c oss - 250 - pf reverse transfer capacitance c rss -75 - pf thermal resistance junction to case r jc - - 2.00 o c/w thermal resistance junction to ambient r ja to-220ab, to-263ab - - 80 o c/w source to drain diode speci?ations parameter symbol test conditions min typ max units source to drain diode voltage v sd i sd = 23a - - 1.5 v diode reverse recovery time t rr i sd = 23a, di sd /dt = 100a/ s--85ns notes: 2. pulse test: pulse width 300ms, duty cycle 2%. 3. repetitive rating: pulse width limited by max junction temperature. see transient thermal impedance curve (figure 3) and peak current capability curve (figure 5). rfp23n06le, RF1S23N06LESM
3 typical performance curves unless otherwise speci?d figure 1. normalized power dissipation vs case temperature figure 2. maximum continuous drain current vs case temperature figure 3. normalized maximum transient thermal impedance figure 4. forward bias safe operating area figure 5. peak current capability t c , case temperature ( o c) power dissipation multiplier 0 0 25 50 75 100 175 0.2 0.4 0.6 0.8 1.0 1.2 125 150 10 5 0 25 50 75 100 125 150 15 25 20 i d , drain current (a) t c , case temperature ( o c) 175 t, rectangular pulse duration (s) 10 -5 10 -3 10 -2 10 -1 10 0 0.01 2 0.1 1 10 -4 10 1 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z jc x r jc + t c p dm t 1 t 2 single pulse z jc , normalized thermal impedance 0.5 0.2 0.1 0.05 0.01 0.02 v ds , drain to source voltage (v) 110 1 100 10 i d , drain current (a) limited by r ds(on) area may be operation in this 100 s 10ms 1ms 500 100 60 200 t c = 25 o c t j = max rated t, pulse width (s) 500 10 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 100 i dm , peak current capability (a) i = i 25 175 - t c 150 for temperatures above 25 o c derate peak current as follows: v gs = 5v thermal impedance may limit current in this region v gs = 10v t c = 25 o c rfp23n06le, RF1S23N06LESM
4 note: refer to intersil application notes an9321 and an9322. figure 6. unclamped inductive switching figure 7. saturation characteristics figure 8. transfer characteristics figure 9. drain to source on resistance vs gate voltage and drain current figure 10. switching time vs gate resistance figure 11. normalized drain to source on resistance vs junction temperature typical performance curves unless otherwise speci?d (continued) 10 100 1 i as , avalanche current (a) t av , time in avalanche (ms) starting t j = 150 o c starting t j = 25 o c t av = (l)(i as )/(1.3*rated bv dss - v dd ) if r = 0 if r 0 t av = (l/r)ln[(i as *r)/(1.3*rated bv dss - v dd ) +1] 0.1 1 10 0.001 0.01 0 10 30 0 1.5 3.0 4.5 6.0 20 50 i d , drain current (a) v ds , drain to source voltage (v) v gs = 3v v gs = 10v v gs = 2.5v v gs = 4v 40 v gs = 3.5v v gs = 4.5v v gs = 5v t c = 25 o c pulse duration = 80 s duty cycle = 0.5% max 0 3 4.5 6 1.5 0 10 20 30 50 175 o c i ds(on) , drain to source current (a) v gs , gate to source voltage (v) -55 o c 25 o c pulse duration = 80 s duty cycle = 0.5% max 40 v dd = 15v 50 100 150 200 0 3 v gs , gate to source voltage (v) r ds(on) , drain to source 2 i d = 46a 3.5 4.5 5 i d = 23a i d = 5.75a i d = 11.5a 4 2.5 pulse duration = 80 s on resistance (m ? ) v dd = 15v duty cycle = 0.5% max 100 20 30 40 50 0 250 200 150 50 0 10 switching time (ns) r gs , gate to source resistance ( ? ) t r t d(off) t f t d(on) v dd = 30v, i d = 23a, r l = 1.30 ? 0.5 1 1.5 2 -80 -40 0 40 80 120 160 normalized drain to source t j , junction temperature ( o c) 2.5 200 pulse duration = 80 s on resistance v gs = 5v, i d = 23a duty cycle = 0.5% max rfp23n06le, RF1S23N06LESM
5 figure 12. normalized gate threshold voltage vs junction temperature figure 13. normalized drain to source breakdown voltage vs junction temperature figure 14. capacitance vs drain to source voltage note: refer to intersil application notes an7254 and an7260. figure 15. normalized switching waveforms for constant gate current test circuits and waveforms figure 16. unclamped energy test circuit figure 17. unclamped energy waveforms typical performance curves unless otherwise speci?d (continued) -80 -40 0 40 80 120 160 normalized gate threshold voltage t j , junction temperature ( o c) 200 2 1 0.5 0 1.5 v gs = v ds , i d = 250 a 1.2 1.0 0.9 0.8 -80 -40 0 40 80 120 160 t j , junction temperature ( o c) normalized drain to source breakdown voltage 200 1.1 i d = 250 a 1200 800 400 0 0 5 10 15 20 25 c, capacitance (pf) c rss 600 c iss c oss v ds , drain to source voltage (v) 200 1000 v gs = 0v, f = 1mhz c iss = c gs + c gd c rss = c gd c oss c ds + c gd 60 45 30 15 0 20 i gref () i gact () --------------------- - t, time ( s) 80 i gref () i g act () --------------------- - 5.00 3.75 2.50 1.25 0 v ds , drain to source voltage (v) v gs , gate to source voltage (v) r l = 2.17 ? i g(ref) = 0.45ma v gs = 5v v dd = bv dss v dd = 0.75 bv dss v dd = 0.50 bv dss v dd = 0.25 bv dss plateau voltages in descending order: v dd = bv dss v dd = bv dss t p v gs 0.01 ? l i as + - v ds v dd r g dut vary t p to obtain required peak i as 0v v dd v ds bv dss t p i as t av 0 rfp23n06le, RF1S23N06LESM
6 figure 18. switching time test circuit figure 19. resistive switching waveforms figure 20. gate charge test circuit figure 21. gate charge waveforms test circuits and waveforms (continued) v gs r l r gs dut + - v dd v ds v gs t on t d(on) t r 90% 10% v ds 90% 10% t f t d(off) t off 90% 50% 50% 10% pulse width v gs 0 0 r l v gs + - v ds v dd dut i g(ref) v dd q g(th) v gs = 2v q g(10) or q g(5) v gs = 5v for q g(tot) v gs = 20v v ds v gs i g(ref) 0 0 v gs = 1v for l 2 devices l 2 devices v gs = 10v v gs = 10v for l 2 devices rfp23n06le, RF1S23N06LESM
7 pspice electrical model subckt 23n06le 2 1 3 ; rev 9/27/95 ca 12 8 1.1e-9 cb 15 14 1.1e-9 cin 6 8 8.5e-10 dbody 7 5 dbodymod dbreak 5 11 dbreakmod dplcap 10 5 dplcapmod ebreak 11 7 17 18 69.6 eds 14 8 5 8 1 egs 13 8 6 8 1 esg 6 10 6 8 1 evthres 6 21 19 8 1 evtemp 20 6 18 22 1 it 8 17 1 ldrain 2 5 1e-9 lgate 1 9 4.4e-9 lsource 3 7 4.5e-9 mmed 16 6 8 8 mmedmod mstro 16 6 8 8 mstromod mweak 16 21 8 8 mweakmod rbreak 17 18 rbreakmod 1 rdrain 50 16 rdrainmod 1.5e-2 rgate 9 20 3.1 rldrain 2 5 10 rlgate 1 9 44 rlsource 3 7 45 rslc1 5 51 rslcmod 1e-6 rslc2 5 50 1e3 rsource 8 7 rsourcemod 9e-3 rvthres 22 8 rvthresmod 1 rvtemp 18 19 rvtempmod 1 s1a 6 12 13 8 s1amod s1b 13 12 13 8 s1bmod s2a 6 15 14 13 s2amod s2b 13 15 14 13 s2bmod vbat 22 19 dc 1 eslc 51 50 value={(v(5,51)/abs(v(5,51)))*(pwr(v(5,51)/(1e-6*70),3.5))} .model dbodymod d (is = 1.3e-12 rs = 7.5e-3 trs1 = 1e-4 trs2 = 3e-6 cjo = 1.07e-9 tt = 4.9e-8 n = 1.03 m = 0.5) .model dbreakmod d (rs = 3.5e-1 trs1 = 1e-4 trs2 = 0) .model dplcapmod d (cjo = 7.5e-10 is = 1e-30 n = 10 m = 0.85) .model mmedmod nmos (vto = 2.0 kp = 4 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u rg = 3.1) .model mstromod nmos (vto = 2.34 kp = 43 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u) .model mweakmod nmos (vto = 1.74 kp = 0.13 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u rg = 31 rs = 0.1) .model rbreakmod res (tc1 = 1.2e-3 tc2 = -5e-7) .model rdrainmod res (tc1 = 9e-3 tc2 = 2e-5) .model rslcmod res (tc1 = 3.5e-3 tc2 = 7e-6) .model rsourcemod res (tc1 = 1e-3 tc2 = 1e-6) .model rvthresmod res (tc1 = -1.8e-3 tc2 = -5.8e-6) .model rvtempmod res (tc1 = -1.7e-3 tc2 = 1e-6) .model s1amod vswitch (ron = 1e-5 roff = 0.1 von = -4.5 voff= -2.8) .model s1bmod vswitch (ron = 1e-5 roff = 0.1 von = -2.8 voff= -4.5) .model s2amod vswitch (ron = 1e-5 roff = 0.1 von = -0.5 voff= 0.5) .model s2bmod vswitch (ron = 1e-5 roff = 0.1 von = 0.5 voff= -0.5) .ends note: for further discussion of the pspice model, consult a new pspice sub-circuit for the power mosfet featuring global temperature options; ieee power electronics specialist conference records, 1991. 18 22 + - 6 8 + - 5 51 + - 19 8 + - 17 18 6 8 + - 5 8 + - rbreak rvtemp vbat rvthres it 17 18 19 22 12 13 15 s1a s1b s2a s2b ca cb egs eds 14 8 13 8 14 13 mweak ebreak dbody rsource source 11 7 3 lsource rlsource cin rdrain evthres 16 21 8 mmed mstro drain 2 ldrain rldrain dbreak dplcap eslc rslc1 10 5 51 50 rslc2 1 gate rgate evtemp 9 esg lgate rlgate 20 + - + - + - 6 rfp23n06le, RF1S23N06LESM
8 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?ation. intersil semiconductor products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/or spec ifications at any time with- out notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is b elieved to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of th ird parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see web site http://www.intersil.com sales of?e headquarters north america intersil corporation p. o. box 883, mail stop 53-204 melbourne, fl 32902 tel: (407) 724-7000 fax: (407) 724-7240 europe intersil sa mercure center 100, rue de la fusee 1130 brussels, belgium tel: (32) 2.724.2111 fax: (32) 2.724.22.05 asia intersil (taiwan) ltd. 7f-6, no. 101 fu hsing north road taipei, taiwan republic of china tel: (886) 2 2716 9310 fax: (886) 2 2715 3029 rfp23n06le, RF1S23N06LESM
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